1. Field of the Invention
The present invention relates to flip-flop circuits, and particularly to flip-flop circuits having a function of diagnosing (testing) a combination circuit.
2. Description of the Background Art
With the higher integration of logic circuits, a diagnosis (test) thereof has become more difficult. In order to diagnose a logic circuit readily, a flip-flop circuit has been developed which serves as a flip-flop in normal operation, and as a shift register in diagnostic operation.
FIG. 7 is a block diagram showing an example of the whole structure of a semiconductor integrated circuit device including flip-flop circuits having a shift function.
A plurality of flip-flop circuits 10a, 10b, 10c and a plurality of combination circuits 20a, 20b, 20c are formed on a semiconductor chip CH. A plurality of input terminals I11 to I15 receiving externally applied signals, and a plurality of output terminals O11 to O14 applying signals to the outside of the chip are also provided on the semiconductor chip CH. A combination circuit, here, means a logic circuit in which an output value at any moment is defined correspondingly to the input value at the moment.
Each of the flip-flop circuits 10a, 10b, 10c has a main data input terminal D receiving main data in normal operation, a diagnosis data input terminal I receiving diagnosis data in diagnostic operation, a main clock input terminal T receiving a main clock signal in normal operation, a shift operation clock input terminal A receiving a shift operation clock signal in diagnostic operation, and a data output terminal Q outputting main data and diagnosis data. Each of the combination circuits 20a, 20b, 20c has data input terminals i1, i2, receiving data and data output terminals o1, o2 outputting data.
FIG. 8 shows a detailed structure of the flip-flop circuits 10a and 10b, 10c. The flip-flop circuit of FIG. 8 is described, for example, by S. Funatsu, N. Wakatsuki and T. Arima, in "Test generation systems in Japan", Proc. 12th Design Automation Conf., pp. 114-122 (1975).
The flip-flop circuit of FIG. 8 includes a first latch circuit L1, a second latch circuit L2, AND gates G1, G2, OR gates G3, G4, and an inverter G5.
The AND gate G1 has one input terminal connected to the main data input terminal D, and the other input terminal connected to the main clock input terminal T. The AND gate G2 has one input terminal connected to the diagnosis data input terminal I, and the other input terminal connected to the shift operation clock input terminal A. An output signal of the AND gate G1 and an output signal of the AND gate G2 are respectively applied to one input terminal and the other input terminal of the OR gate G3. The OR gate G4 has one input terminal connected to a main clock input terminal T, and the other input terminal connected to the shift operation clock input terminal A.
An output signal of the OR gate G3 is applied to a data input terminal D1 of the first latch circuit L1, and an output signal of the OR gate G4 is applied to a clock input terminal T1 of the first latch circuit L1. A data output terminal Q1 of the first latch circuit L1 is connected to a data input terminal D2 of the second latch circuit L2. An output signal of the OR gate G4 is applied through the inverter G5 to a clock input terminal T2 of the second latch circuit L2. A data output terminal Q2 of the second latch circuit L2 is connected to the data output terminal Q.
The first latch circuit L1 is a high enable D type latch circuit. Specifically, when a potential of the clock input terminal T1 becomes high, data applied to the data input terminal D1 is output from the data output terminal Q1, and when the potential of the clock input terminal T1 becomes low, the data is held therein. The second latch circuit L2 is also a high enable D type latch circuit.
The operations of the flip-flop circuit of FIG. 8 will now be described with reference to a logic state chart of. FIG. 9.
In normal operation, a potential of the shift operation clock input terminal A is fixed to low (L). A main clock signal CLK applied to the shift clock input terminal T is applied through the OR gate G4 to the clock input terminal T1 of the first latch circuit L1, and an inverted signal of the main clock signal CLK is applied through the inverter G5 to the clock input terminal T2 of the second latch circuit L2.
As a result, data provided from the first latch circuit L1 is applied to the second latch circuit L2, and main data MD applied to the main data input terminal D is applied through the AND gate G1 and the OR gate G3 to the data input terminal D1 of the first latch circuit L1. As described above, the first and second latch circuits L1, L2 serve as flip-flops.
In shift operation, a potential of the main clock input terminal D is fixed to low (L), and a shift operation clock signal SCLK1 is applied to the shift operation clock input terminal A. The shift operation clock signal SCLK1 is applied through the OR gate G4 to the clock input terminal T1 of the first latch circuit L1, and an inverted signal of the shift operation clock signal SCLK1 is applied through the inverter G5 to the clock input terminal T2 of the second latch circuit L2.
Accordingly, data provided from the first latch circuit L1 is applied to the second latch circuit L2, and diagnosis data (test data) TD applied to the diagnosis data input terminal I is applied through the AND gate G2 and the OR gate G3 to the data input terminal D1 of the first latch circuit L1. As described above, the first and second latch circuits L1, L2 serve as shift registers.
A procedure of diagnosing a combination circuit included in the semiconductor integrated circuit device shown in FIG. 7 will be hereinafter described. Here as an example, the operations in the diagnosis of the combination circuit 20b will be described.
First, a potential of the input terminal I14 is set to low to set potentials of the main clock input terminals T of the flip-flop circuits 10a, 10b, 10c to low. In addition, the shift operation clock signal SCLK1 is applied to the input terminal I15 to be applied to the shift operation clock input terminals A of the flip-flop circuits 10a, 10b, 10c. Then, the flip-flop circuits 10a, 10b, 10c carry out the shift operation.
The shift operation causes the diagnosis data TD of the input terminal I13 to be set to the second latch circuit L2 in the flip-flop circuit 10b through the flip-flop circuit 10a, whereby the diagnosis data TD is output from the data output terminal Q of the flip-flop circuit 10b, and applied to the data input terminal i2 of the combination circuit 20b.
Next, a potential of the input terminal I15 is set to low to set potentials of the shift operation clock input terminals A of the flip-flop circuits 10a, 10b, 10c to low. In addition, the main clock signal CLK is applied to the input terminal I14 to be applied to the main clock input terminals T of the flip-flop circuits 10a, 10b, 10c. Then, the flip-flop circuits 10a, 10b, 10c carry out the normal operation.
The normal operation causes the data provided from the data output terminal o2 of the combination circuit 20b to be taken in the first latch circuit L1 in the flip-flop circuit 10c.
Finally, the data held in the first latch circuit L1 in the flip-flop circuit 10c is shifted to the second latch circuit L2 of the flip-flop circuit 10c by shift operation, and output from the output terminal O13.
In this manner, the diagnosis data is set to the combination circuit 20b, and the data provided from the combination circuit 20b is observed. The combination circuits 20a, 20c can be diagnosed similarly.
As described above, in a semiconductor integrated circuit device including the flip-flop circuit of FIG. 8, it is necessary to set the potential of the main clock input terminal T of each flip-flop circuits to low through the input terminal I14 in shift operation. However, in the structure where data provided from a combination circuit is as a clock signal applied to the main clock input terminal T of each flip-flop circuit, the operations of the first and second latch circuits L1, L2 of each flip-flop circuit cannot be externally controlled. Therefore, the combination circuits cannot be diagnosed in such a structure.
If a set/reset signal input terminal supplied with a set/reset signal from a combination circuit is provided in each flip-flop circuit, each flip-flop circuit might be set or reset in shift operation,irrespective of the shift operation. For this reason, a set/reset signal input terminal is not provided in a flip-flop circuit.
In addition, if a timing of a rise of the shift operation clock signal SCLK1 applied to the clock input terminal T1 of the first latch circuit L1 becomes earlier than a timing of a fall of the inverted signal/SCLK1 applied to the clock input terminal T2 of the second latch circuit L2 in shift operation, the first and second latch circuits L1, L2 are simultaneously enabled for a certain period.
As a result, before the second latch circuit L2 holds the data before the change, the data after the change applied to the data input terminal D1 of the first latch circuit L1 is transferred through the first and second latch circuits L1, L2 to the data output terminal Q2 of the second latch circuit L2. This is referred to as inphase transfer. In the flip-flop circuits of FIG. 8, a problem exists that clock skew management for avoiding inphase transfer and ensuring shift operation is difficult to be carried out.